//=== Ports === #define SDI_PORT PORTA #define SDI_DDR DDRA #define SCK_PORT PORTD #define SCK_DDR DDRD #define CS_PORT PORTD #define CS_DDR DDRD #define SDO_PIN PINA #define SDO_DDR DDRA // === Pins === #define SDI 1 #define SCK 1 #define CS 0 #define SDO 0 //=== Macros === // SDO //#define clr_SDO(); SDO_PORT&=~(1< 3903) // 868...MHz { freq = 3903; } */ rf12_trans(0xA000 | freq); //set freq } void rf12_setbaud(unsigned short baud) { if (baud < 664) { baud = 664; } if (baud < 5400) // Baudrate= 344827,58621/(R+1)/(1+CS*7) { rf12_trans(0xC680 | ((43104 / baud) - 1)); // R=(344828/8)/Baud-1 } else { rf12_trans(0xC600 | ((344828UL / baud) - 1)); // R=344828/Baud-1 } } void rf12_setpower(unsigned char power, unsigned char mod) { rf12_trans(0x9800 | (power & 7) | ((mod & 15) << 4)); } void rf12_ready(void) { unsigned long timeout = 0; clr_SDI(); clr_CS(); asm("nop"); //wait until FIFO ready or timeout while (!(SDO_PIN & (1 << SDO))) { if (((timeout++) > 70000)) { break; } } } /* void rf12_txdata(unsigned char *data, unsigned char number) { unsigned char i; rf12_trans(0x8238); // TX on rf12_ready(); rf12_trans(0xB8AA); rf12_ready(); rf12_trans(0xB8AA); rf12_ready(); rf12_trans(0xB8AA); rf12_ready(); rf12_trans(0xB82D); rf12_ready(); rf12_trans(0xB8D4); for (i = 0; i < number; i++) { rf12_ready(); rf12_trans(0xB800 | (*data++)); } rf12_ready(); rf12_trans(0xB800); rf12_ready(); _delay_us(10); rf12_trans(0x8208); // TX off } */ void rf12_rxdata(unsigned char *data, unsigned char number) { unsigned char i; rf12_trans(0x82C8); // RX on rf12_trans(0xCA81); // set FIFO mode rf12_trans(0xCA83); // enable FIFO for (i = 0; i < number; i++) { rf12_ready(); *data++ = rf12_trans(0xB000); } rf12_trans(0x8208); // RX off }